Protocol

UCIe

Universal Chiplet Interconnect Express

Lab ready Full lab

Universal Chiplet Interconnect Express — a die-to-die standard with streaming and protocol mappings (including PCIe/CXL). Advanced packaging electricals and retimers dominate physical design. It targets multi-die compositions rather than board-level cables.

Domains

Tags

chipletdie-to-diepackaginginterconnect

Sources

  • UCIe Specification

Related protocols

CXL

Lab ready

Compute Express Link — a cache-coherent interconnect riding PCIe PHY for memory expanders and accelerators. .io, .cache, and .mem protoco…

aistorage

PCI Express

Lab ready

PCI Express — packetized serial I/O with lanes, LTSSM link training, and TLP/DLLP layers. Gen5/Gen6 rates and retimers define reach; ACS …

aistorageembedded