Embedded

Classical Controller Area Network with 11-bit and 29-bit identifiers, CSMA/CR arbitration, and up to 8 data bytes. Dominant/recessive wir…

CAN Flexible Data-Rate extends classical CAN with up to 64 data bytes and a faster data-phase bitrate after arbitration. BRS and ESI bits…

Asynchronous character framing with start bit, 5–9 data bits, optional parity, and one or two stop bits. RS-232 defines voltage levels an…

Two-wire multi-master bus (SCL/SDA) with open-drain wired-AND, 7/10-bit addressing, and ACK bits after every byte. Start/stop conditions …

Full-duplex synchronous bus with SCLK, MOSI, MISO, and per-device chip select. Mode is defined by CPOL/CPHA (or mode 0–3); there is no st…

ARM two-pin debug protocol (SWDIO/SWCLK) replacing full JTAG for Cortex-M. Packets select DP/AP registers for memory access, breakpoints,…

Binary Modbus ADU on serial lines: address, PDU (function + data), and CRC-16. Silent intervals of 3.5 character times delimit frames; fu…

Differential multi-drop serial physical layer used under Modbus RTU, Profibus, and many industrial buses. Half-duplex pairs need directio…

Boundary-scan and debug TAP with TMS/TCK/TDI/TDO state machine. Chains, IR/DR lengths, and adaptive clocking matter when probing multi-ch…

Single-wire half-duplex bus with parasite power for sensors and ID chips. Presence pulse, ROM commands, and strict slot timing are the us…

I²C-derived management bus with timeouts, PEC, and defined commands for power/thermal devices. Stricter electrical and timing rules than …

SPI variant with 1/2/4 IO lines for flash and peripherals. Address/command phases and dummy cycles dominate throughput; mode and DDR opti…

ARM Cortex single-pin async trace for printf-style ITM packets and event counters. Baud must match debugger; Manchester vs UART encoding …

Single-edge nibble transmission for automotive sensors. Tick time, sync pulse, and CRC nibble framing are fixed; Fast/Slow channels carry…

USB class that presents a virtual COM port over bulk endpoints. Line coding and control lines map UART semantics onto USB transfers.

Timed pulse encodings for actuators, RC control, and sensing. Duty cycle, period stability, and edge polarity define the information chan…

Command set layered on SMBus for digital power converters: voltage setpoints, telemetry, sequencing, and fault logs. Transaction types (w…

Management interface for Ethernet PHYs: MDC clock plus bidirectional MDIO with preamble, start, op, PHYAD, and REGAD fields. Clause 22 ex…

SD card command/response/data protocol extended so non-memory functions (Wi-Fi, GPS, Bluetooth) enumerate as SDIO devices. CMD/DAT lines,…

CAN application profile (CiA 301) built around an Object Dictionary, PDOs for realtime process data, SDOs for configuration, and an NMT s…

Lighting-control bus (IEC 62386) with Manchester encoding, short addresses, and group/scene concepts. Forward frames command ballasts and…

Short-range low-power radio using advertising, connections, and GATT attribute tables for application data. PHY rates (1M/2M/Coded), ATT …

Nordic Semiconductor short-range proprietary packet modes, including Enhanced ShockBurst, for low-latency links on nRF radios. Address fi…

Host-centric shared bus with control, bulk, interrupt, and isochronous transfers at low/full/high speed. Device identity lives in descrip…

USB class for keyboards, mice, gamepads, and vendor-defined reports. Report descriptors declare bit-level layouts that hosts parse into i…

ASCII talker sentence protocol for GNSS and marine instruments, traditionally over 4800 8N1 serial (higher rates are common now). Sentenc…

PCI Express — packetized serial I/O with lanes, LTSSM link training, and TLP/DLLP layers. Gen5/Gen6 rates and retimers define reach; ACS …